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Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp ADN2819
FEATURES
Meets SONET requirements for jitter transfer/generation/tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: 100 mV 1.9 GHz minimum bandwidth Patented clock recovery architecture Loss of signal detect range: 3 mV to 15 mV Single reference clock frequency for all rates, including 15/14 (7%) wrapper rate Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz REFCLK LVPECL/LVDS/LVCMOS/LVTTL compatible inputs (LVPECL/LVDS only at 155.52 MHz) 19.44 MHz oscillator on-chip to be used with external crystal Loss of lock indicator Loopback mode for high speed test data Output squelch and bypass features Single-supply operation: 3.3 V Low power: 540 mW typical 7 mm x 7 mm 48-lead LFCSP
PRODUCT DESCRIPTION
The ADN2819 provides the receiver functions of quantization, signal level detect, and clock and data recovery at rates of OC-3, OC-12, OC-48, Gigabit Ethernet, and 15/14 FEC rates. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for -40C to +85C ambient temperature, unless otherwise noted. The device is intended for WDM system applications, and can be used with either an external reference clock or an on-chip oscillator with external crystal. Both native rates and 15/14 rate digital wrappers are supported by the ADN2819, without any change of reference clock. This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power, fiber optic receiver. The receiver front end signal detect circuit indicates when the input signal level has fallen below a user-adjustable threshold. The signal detect circuit has hysteresis to prevent chatter at the output. The ADN2819 is available in a compact 7 mm x 7 mm, 48-lead chip scale package.
APPLICATIONS
SONET OC-3/-12/-48, SDH STM-1/-4/-16, GbE and 15/14 FEC rates WDM transponders Regenerators/repeaters Test equipment Backplane applications
FUNCTIONAL BLOCK DIAGRAM
SLICEP/N VCC VEE CF1 CF2 LOL
2 PIN QUANTIZER NIN
ADN2819
LOOP FILTER /n XTAL OSC
2 2
REFSEL[0..1] REFCLKP/N XO1
PHASE SHIFTER
PHASE DET.
LOOP FILTER
VCO
FREQUENCY LOCK DETECTOR
XO2 VREF LEVEL DETECT DATA RETIMING 2 THRADJ SDOUT DATAOUTP/N 2 CLKOUTP/N SEL[0..2] DIVIDER 1/2/4/16 FRACTIONAL DIVIDER 3 REFSEL
02999-0-001
Figure 1. Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
ADN2819 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Definition of Terms.......................................................................... 9 Maximum, Minimum, and Typical Specifications ................... 9 Input Sensitivity and Input Overdrive....................................... 9 Single-Ended vs. Differential ...................................................... 9 LOS Response Time ................................................................... 10 Jitter Specifications..................................................................... 10 Theory of Operation ...................................................................... 12 Functional Description .................................................................. 14 Multirate Clock and Data Recovery......................................... 14 Limiting Amplifier ..................................................................... 14 Slice Adjust .................................................................................. 14 Loss of Signal (LOS) Detector .................................................. 14 Reference Clock.......................................................................... 14 Lock Detector Operation .......................................................... 15 Squelch Mode ............................................................................. 16 Test Modes: Bypass and Loopback........................................... 16 Applications Information .............................................................. 17 PCB Design Guidelines ............................................................. 17 Choosing AC-Coupling Capacitors ......................................... 19 DC-Coupled Application .......................................................... 20 LOL Toggling During Loss of Input Data............................... 20 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 21
REVISION HISTORY
5/04--Data Sheet Changed from Rev. A to Rev. B Updated Format..............................................................Universal Changes to Specifications ............................................................ 3 Changes to Table 7 and Table 8................................................. 15 Updated Outline Dimensions ................................................... 21 Changes to Ordering Guide ...................................................... 21 1/03--Data Sheet Changed from Rev. 0 to Rev. A Changes to Table IV ................................................................... 12 Updated OUTLINE DIMENSIONS ........................................ 16
Rev. B | Page 2 of 24
ADN2819 SPECIFICATIONS
Table 1. TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 4.7 F, SLICEP = SLICEN = VCC, unless otherwise noted.
Parameter QUANTIZER--DC CHARACTERISTICS Input Voltage Range Peak-to-Peak Differential Input Input Common-Mode Level Differential Input Sensitivity Input Overdrive Input Offset Input rms Noise QUANTIZER--AC CHARACTERISTICS Upper -3 dB Bandwidth Small Signal Gain S11 Input Resistance Input Capacitance Pulse Width Distortion2 QUANTIZER SLICE ADJUSTMENT Gain Control Voltage Range Slice Threshold Offset LEVEL SIGNAL DETECT (SDOUT) Level Detect Range (See Figure 4) Conditions @ PIN or NIN, dc-coupled DC-coupled (See Figure 28) PIN-NIN, ac-coupled1, BER = 1 x 10-10 See Figure 8 BER = 1 x 10-10 Min 0 0.4 4 2 500 244 1.9 54 -15 100 0.65 10 0.11 -0.8 1.3 0.20 0.30 +0.8 VCC 10 5 Typ Max 1.2 2.4 Unit V V V mV p-p mV p-p V V rms GHz dB dB pF ps V/V V V mV mV mV mV s dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
Differential @ 2.5 GHz Differential
SLICEP-SLICEN = 0.5 V SLICEP-SLICEN @ SLICEP or SLICEN
1.0 RTHRESH = 2 RTHRESH = 20 k RTHRESH = 90 k DC-coupled OC-48, PRBS 223 RTHRESH = 2 k RTHRESH = 20 k RTHRESH = 90 k OC-12, PRBS 223 RTHRESH = 2 k RTHRESH = 20 k RTHRESH = 90 k RTHRESH = 90 k @ 25C OC-3, PRBS 223 RTHRESH = 2 k RTHRESH = 20 k RTHRESH = 90 k RTHRESH = 90 k @ 25C OC-48, PRBS 27 RTHRESH = 2 k RTHRESH = 20 k RTHRESH = 90 k OC-12, PRBS 27 RTHRESH = 2 k RTHRESH = 20 k RTHRESH = 90 k 9.4 2.5 0.7 0.1 5.6 3.9 3.2 4.7 1.8 4.8 3.6 13.3 5.3 3.0 0.3 6.6 6.2 6.7 6.4 6.0 6.3 6.9 6.2 5.6 5.6 6.6 6.6 6.2 6.7 6.6 6.2 6.7 18.0 7.6 5.2 5 7.8 8.5 9.9 7.8 10.0 8.9 8.5
Response Time Hysteresis (Electrical)
3.4 5.6 3.9 3.2 5.7 3.9 3.2
9.9 7.8 8.5 9.9 7.8 8.5 9.9
Rev. B | Page 3 of 24
ADN2819
Parameter Hysteresis (Electrical) (continued) Conditions OC-3, PRBS 27 RTHRESH = 2 k RTHRESH = 20 k RTHRESH = 90 k From fVCO error > 1000 ppm 3.0 150 PIN-NIN = 10 mV p-p OC-48 GbE OC-12 OC-3 OC-48 OC-12 OC-3 OC-48, 12 kHz-20 MHz OC-12, 12 kHz-5 MHz 0.02 OC-3, 12 kHz-1.3 MHz 0.02 Jitter Tolerance OC-48 (See Figure 14) 600 Hz3 6 kHz3 100 kHz 1 MHz3 GbE (OC-24) (See Figure 14) 300 Hz3 3 kHz3 50 kHz 500 kHz3 OC-12 (See Figure 14) 30 Hz3 300 Hz 25 kHz 250 kHz3 OC-3 (See Figure 14) 30 Hz3 300 Hz3 6500 Hz 65 kHz3 VSE (See Figure 7) VDIFF (See Figure 7) VOH VOL, referred to VCC 20%-80% 80%-20% 92 20 5.5 1.0 16 16 7.7 2.2 100 44 5.8 1.0 50 23.5 6.0 1.0 300 600 -0.60 455 910 VCC 600 1200 -0.30 150 150 Min 5.4 4.6 3.9 Typ 6.6 6.4 6.8 60 3.3 164 590 310 140 48 0.025 0.004 0.002 0.05 Max 7.7 8.2 9.7 Unit dB dB dB mV V mA kHz kHz kHz kHz dB dB dB UI rms UI p-p UI rms UI p-p UI rms UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p mV mV V V ps ps
LOSS OF LOCK DETECTOR (LOL) Loss of Lock Response Time POWER SUPPLY VOLTAGE POWER SUPPLY CURRENT PHASE-LOCKED LOOP CHARACTERISTICS Jitter Transfer BW
3.6 215 880 480 200 85
Jitter Peaking
Jitter Generation
0.003 0.09 0.002 0.04 0.002 0.04
CML OUTPUTS (CLKOUTP/N, DATAOUTP/N) Single-Ended Output Swing Differential Output Swing Output High Voltage Output Low Voltage Rise Time Fall Time
Rev. B | Page 4 of 24
ADN2819
Parameter Setup Time Conditions TS (See Figure 3) OC-48 GbE OC-12 OC-3 TH (See Figure 3) OC-48 GbE OC-12 OC-3 @ REFCLKP or REFCLKN DC-coupled, single-ended CML inputs Min 140 350 750 3145 150 350 750 3150 0 100 VCC/2 0.8 VIH VIL VIN = 0.4 V or VIN = 2.4 V VIN = 0.4 V or VIN = 2.4 V VOH, IOH = -2.0 mA VOL, IOL = +2.0 mA 2.0 -5 -5 2.4 0.4 V 0.8 +5 +50 V A A V V VCC Typ Max Unit ps ps ps ps ps ps ps ps V mV V V
Hold Time
REFCLK DC INPUT CHARACTERISTICS Input Voltage Range Peak-to-Peak Differential Input Common-Mode Level TEST DATA DC INPUT CHARACTERISTICS4 (TDINP/N) Peak-to-Peak Differential Input Voltage LVTTL DC INPUT CHARACTERISTICS Input High Voltage Input Low Voltage Input Current Input Current (SEL0 and SEL1 Only)5 LVTTL DC OUTPUT CHARACTERISTICS Output High Voltage Output Low Voltage
1 2
PIN and NIN should be differentially driven, ac-coupled for optimum sensitivity. PWD measurement made on quantizer outputs in bypass mode. 3 Jitter tolerance measurements are equipment limited. 4 TDINP/N are CML inputs. If the drivers to the TDINP/N inputs are anything other than CML, they must be ac-coupled. 5 SEL0 and SEL1 have internal pull-down resistors, causing higher IIH.
Rev. B | Page 5 of 24
ADN2819 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage (VCC) Minimum Input Voltage (All Inputs) Maximum Input Voltage (All Inputs) Maximum Junction Temperature Storage Temperature Lead Temperature (Soldering 10 sec) Rating 5.5 V VEE - 0.4 V VCC + 0.4 V 165C -65C to +150C 300C
THERMAL CHARACTERISTICS
Thermal Resistance
48-lead LFCSP, 4-layer board with exposed paddle soldered to VCC JA = 25C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. B | Page 6 of 24
ADN2819 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 LOOPEN 47 VCC 46 VEE 45 SDOUT 44 BYPASS 43 VEE 42 VEE 41 CLKOUTP 40 CLKOUTN 39 SQUELCH 38 DATAOUTP 37 DATAOUTN
THRADJ 1 VCC 2 VEE 3 VREF 4 PIN 5 NIN 6 SLICEP 7 SLICEN 8 VEE 9 LOL 10 XO1 11 XO2 12
PIN 1 INDICATOR
ADN2819
TOPVIEW
36 VCC 35 VCC 34 VEE 33 VEE 32 SEL0 31 SEL1 30 SEL2 29 VEE 28 VCC 27 VEE 26 VCC 25 CF2
REFCLKN 13 REFCLKP 14 REFSEL 15 VEE 16 TDINP 17 TDINN 18 VEE 19 VCC 20 CF1 21 VEE 22 REFSEL1 23 REFSEL0 24
Figure 2. 48-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin Number 1 2, 26, 28, Pad 3, 9, 16, 19, 22, 27, 29, 33, 34, 42, 43, 46 4 5 6 7 8 10 11 12 13 14 15 17 18 20, 47 21 23 24 25 30 31 32 35, 36 37 38 39 40 41 44 45 48 Mnemonic THRADJ VCC VEE VREF PIN NIN SLICEP SLICEN LOL XO1 XO2 REFCLKN REFCLKP REFSEL TDINP TDINN VCC CF1 REFSEL1 REFSEL0 CF2 SEL2 SEL1 SEL0 VCC DATAOUTN DATAOUTP SQUELCH CLKOUTN CLKOUTP BYPASS SDOUT LOOPEN Type1 AI P P AO AI AI AI AI DO AO AO DI DI DI AI AI P AO DI DI AO DI DI DI P DO DO DI DO DO DI DO DI Description LOS Threshold Setting Resistor. Analog Supply. Ground. Internal VREF Voltage. Decouple to GND with 0.1 F capacitor. Differential Data Input. Differential Data Input. Differential Slice Level Adjust Input. Differential Slice Level Adjust Input. Loss of Lock Indicator. LVTTL active high. Crystal Oscillator. Crystal Oscillator. Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz). Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz). Reference Source Select. 0 = on-chip oscillator with external crystal; 1 = external clock source, LVTTL. Differential Test Data Input. CML. Differential Test Data Input. CML. Digital Supply. Frequency Loop Capacitor. Reference Frequency Select (See Table 6) LVTTL. Reference Frequency Select (See Table 6) LVTTL. Frequency Loop Capacitor. Data Rate Select (See Table 5) LVTTL. Data Rate Select (See Table 5) LVTTL. Data Rate Select (See Table 5) LVTTL. Output Driver Supply. Differential Retimed Data Output. CML. Differential Retimed Data Output. CML. Disable Clock and Data Outputs. Active high. LVTTL. Differential Recovered Clock Output. CML. Differential Recovered Clock Output. CML. Bypass CDR Mode. Active high. LVTTL. Loss of Signal Detect Output. Active high. LVTTL. Enable Test Data Inputs. Active high. LVTTL.
1
Type: P = Power, AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output.
Rev. B | Page 7 of 24
02999-B-002
ADN2819
CLKOUTP TS DATAOUTP/N TH
02999-B-003
Figure 3. Output Timing
18 THRADJ RESISTOR VS. LOS TRIP POINT 16 14 12 10
mV
8 6 4 2 0 0 10 20 30 40 50 60 RESISTANCE (k) 70 80 90 100
02999-B-004
Figure 4. LOS Comparator Trip Point Programming
10 9 8 7
18 16 14 12
FREQUENCY
6 5 4 3 2 1
02999-B-005
FREQUENCY
10 8 6 4 2 0
02999-B-006
0
0
1
2
3
4 5 6 7 HYSTERESIS (dB)
8
9
10
0
1
2
3
4
5
6
7
8
9
10
HYSTERESIS (dB)
Figure 5. LOS Hysteresis OC-3, -40C, 3.6 V, 223 - 1 PRBS Input Pattern, RTH = 90 k
Figure 6. LOS Hysteresis OC-12, -40C, 3.6 V, 223 - 1 PRBS Input Pattern, RTH = 90 k
OUTP VCML OUTN OUTP-OUTN
02999-B-007
VSE
VSE 0V
VDIFF
Figure 7. Single-Ended vs. Differential Output Specifications
Rev. B | Page 8 of 24
ADN2819 DEFINITION OF TERMS
MAXIMUM, MINIMUM, AND TYPICAL SPECIFICATIONS
Specifications for every parameter are derived from statistical analyses of data taken on multiple devices from multiple wafer lots. Typical specifications are the mean of the distribution of the data for that parameter. If a parameter has a maximum (or a minimum), that value is calculated by adding to (or subtracting from) the mean six times the standard deviation of the distribution. This procedure is intended to tolerate production variations. If the mean shifts by 1.5 standard deviations, the remaining 4.5 standard deviations still provide a failure rate of only 3.4 parts per million. For all tested parameters, the test limits are guardbanded to account for tester variation and therefore guarantee that no device is shipped outside of data sheet specifications.
SINGLE-ENDED VS. DIFFERENTIAL
AC-coupling is typically used to drive the inputs to the quantizer. The inputs are internally dc biased to a commonmode potential of ~0.6 V. Driving the ADN2819 single-ended and observing the quantizer input with an oscilloscope probe at the point indicated in Figure 9 shows a binary signal with an average value equal to the common-mode potential and instantaneous values above and below the average value. It is convenient to measure the peak-to-peak amplitude of this signal and to call the minimum required value the quantizer sensitivity. Referring to Figure 8, since both positive and negative offsets need to be accommodated, the sensitivity is twice the overdrive.
10mV p-p VREF SCOPE PROBE PIN
INPUT SENSITIVITY AND INPUT OVERDRIVE
Sensitivity and overdrive specifications for the quantizer involve offset voltage, gain, and noise. The relationship between the logic output of the quantizer and the analog voltage input is shown in Figure 8. For a sufficiently large positive input voltage, the output is always Logic 1; similarly for negative inputs, the output is always Logic 0. However, the transitions between output Logic Levels 1 and 0 are not at precisely defined input voltage levels, but occur over a range of input voltages. Within this zone of confusion, the output may be either 1 or 0, or it may even fail to attain a valid logic state. The width of this zone is determined by the input voltage noise of the quantizer. The center of the zone of confusion is the quantizer input offset voltage. Input overdrive is the magnitude of signal required to guarantee the correct logic level with 1 x 10-10 confidence level.
OUTPUT 1 NOISE
ADN2819
+
QUANTIZER
50 VREF
50
02999-B-009
Figure 9. Single-Ended Sensitivity Measurement
5mV p-p VREF SCOPE PROBE PIN
ADN2819
+
QUANTIZER NIN
50
0
50
02999-B-010
VREF
OFFSET OVERDRIVE SENSITIVITY (2x OVERDRIVE)
INPUT (V p-p)
02999-B-008
Figure 10. Differential Sensitivity Measurement
Figure 8. Input Sensitivity and Input Overdrive
Driving the ADN2819 differentially (see Figure 10), sensitivity seems to improve by observing the quantizer input with an oscilloscope probe. This is an illusion caused by the use of a single-ended probe. A 5 mV p-p signal appears to drive the ADN2819 quantizer. However, the single-ended probe measures only half the signal. The true quantizer input signal is twice this value since the other quantizer input is complementary to the signal being observed.
Rev. B | Page 9 of 24
ADN2819
LOS RESPONSE TIME
JITTER GAIN (dB)
The LOS response time is the delay between the removal of the input signal and indication of loss of signal (LOS) at SDOUT. The ADN2819's response time is 300 ns typ when the inputs are dc-coupled. In practice, the time constant of ac-coupling at the quantizer input determines the LOS response time.
0.1
SLOPE = -20dB/DECADE ACCEPTABLE RANGE
JITTER SPECIFICATIONS
The ADN2819 CDR is designed to achieve the best bit-errorrate (BER) performance, and has exceeded the jitter transfer, generation, and tolerance specifications proposed for SONET/SDH equipment defined in the Telcordia Technologies specification. Jitter is the dynamic displacement of digital signal edges from their long-term average positions measured in UI (unit intervals), where 1 UI = 1 bit period. Jitter on the input data can cause dynamic phase errors on the recovered clock sampling edge. Jitter on the recovered clock causes jitter on the retimed data. The following sections summarize the specifications of the jitter generation, transfer, and tolerance in accordance with the Telcordia document (GR-253-CORE, Issue 3, September 2000) for the optical interface at the equipment level, and the ADN2819 performance with respect to those specifications.
fC
JITTER FREQUENCY (kHz)
02999-B-011
Figure 11. Jitter Transfer Curve
Jitter Tolerance
Jitter tolerance is defined as the peak-to-peak amplitude of the sinusoidal jitter applied on the input signal that causes a 1 dB power penalty. This is a stress test that is intended to ensure no additional penalty is incurred under the operating conditions (see Figure 12). Figure 13 shows the typical OC-48 jitter tolerance performance of the ADN2819.
INPUT JITTER AMPLITUDE (UI)
15 SLOPE = -20dB/DECADE
Jitter Generation
Jitter generation specification limits the amount of jitter that can be generated by the device with no jitter and wander applied at the input. For OC-48 devices, the band-pass filter has a 12 kHz high-pass cutoff frequency, with a roll-off of 20 dB/decade and a low-pass cutoff frequency of at least 20 MHz. The jitter generated should be less than 0.01 UI rms and 0.1 UI p-p.
1.5
f0
f1
f2
f3
f4
JITTER FREQUENCY (Hz)
Figure 12. SONET Jitter Tolerance Mask
100
Jitter Transfer
AMPLITUDE (UI p- p)
Jitter transfer function is the ratio of the jitter on the output signal to the jitter applied on the input signal versus the frequency. This parameter measures the limited amount of jitter on an input signal that can be transferred to the output signal (see Figure 11).
ADN2819
10
1
OC-48 SONET MASK
0.1 1 10 100 1k 10k 100k 1M 10M MODULATION FREQUENCY (Hz)
Figure 13. OC-48 Jitter Tolerance Curve
Rev. B | Page 10 of 24
02999-B-013
02999-B-012
0.15
ADN2819
OC3_JIT_TOLERANCE GBE_JIT_TOLERANCE OC3_JIT_TRANSFER GBE_JIT_TRANSFER 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 -9.0 -9.5 -10.0 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M
02999-B-014
OC12_JIT_TOLERANCE OC48_JIT_TOLERANCE OC12_JIT_TRANSFER OC48_JIT_TRANSFER
Figure 14. Jitter Transfer and Jitter Tracking BW
Table 4. Jitter Transfer and Tolerance: SONET Spec vs. ADN2819
Jitter Transfer ADN2819 Implementation SONET Spec (fC) (kHz) Margin 2 MHz 590 3.4 500 kHz 140 3.6 130 kHz 48 2.7 Mask Corner Frequency 1 MHz 250 kHz 65 kHz Jitter Tolerance SONET Spec ADN2819 (UI p-p) (UI p-p) 0.15 1.0 0.15 1.0 0.15 1.0 Implementation Margin1 6.67 6.67 6.67
Rate OC-48 OC-12 OC-3
ADN2819 4.8 MHz 4.8 MHz 600 kHz
1
Jitter tolerance measurements limited by test equipment capabilities.
Rev. B | Page 11 of 24
ADN2819 THEORY OF OPERATION
The ADN2819 is a delay-locked and phase-locked loop circuit for clock recovery and data retiming from an NRZ encoded data stream. The phase of the input data signal is tracked by two separate feedback loops that share a common control voltage. A high speed delay-locked loop path uses a voltage controlled phase shifter to track the high frequency components of the input jitter. A separate phase control loop, comprised of the VCO, tracks the low frequency components of the input jitter. The initial frequency of the VCO is set by a third loop that compares the VCO frequency with the reference frequency and sets the coarse tuning voltage. The jitter tracking phase-locked loop controls the VCO by the fine tuning control. The delay- and phase-locked loops together track the phase of the input data signal. For example, when the clock lags input data, the phase detector drives the VCO to a higher frequency and increases the delay through the phase shifter. Both of these actions serve to reduce the phase error between the clock and data. The faster clock picks up phase while the delayed data loses phase. Since the loop filter is an integrator, the static phase error is driven to zero. Another view of the circuit is that the phase shifter implements the zero required for the frequency compensation of a secondorder phase-locked loop. This zero is placed in the feedback path and therefore does not appear in the closed-loop transfer function. Jitter peaking in a conventional second-order phaselocked loop is caused by the presence of this zero in the closedloop transfer function. Since this circuit has no zero in the closed-loop transfer, jitter peaking is minimized. The delay- and phase-locked loops together simultaneously provide wideband jitter accommodation and narrow-band jitter filtering. The linearized block diagram in Figure 15 shows that the jitter transfer function, Z(s)/X(s), is a second-order low-pass providing excellent filtering. Note that the jitter transfer has no zero, unlike an ordinary second-order phase-locked loop. This means the main PLL loop has low jitter peaking (see Figure 16), which makes this circuit ideal for signal regenerator applications where jitter peaking in a cascade of regenerators can contribute to hazardous jitter accumulation.
psh X(s) e(s) d/sc o/s INPUT DATA
1/n Z(s) RECOVERED CLOCK d = PHASE DETECTOR GAIN o = VCO GAIN c = LOOP INTEGRATOR psh = PHASE SHIFTER GAIN n = DIVIDE RATIO JITTER TRANSFER FUNCTION Z(s) 1 = cn n psh X(s) s2 +s +1 do o TRACKING ERROR TRANSFER FUNCTION e(s) = X(s) s2 do d psh + cn c
02999-B-015
s2 + s
Figure 15. PLL/DLL Architecture
The error transfer, e(s)/X(s), has the same high-pass form as an ordinary phase-locked loop. This transfer function is free to be optimized to give excellent wideband jitter accommodation since the jitter transfer function, Z(s)/X(s), provides the narrowband jitter filtering. See Table 4 for error transfer bandwidths and jitter transfer bandwidths at the various data rates. The delay-locked and phase-locked loops contribute to overall jitter accommodation. At low frequencies of input jitter on the data signal, the integrator in the loop filter provides high gain to track large jitter amplitudes with small phase error. In this case, the VCO is frequency modulated, and jitter is tracked as in an ordinary phase-locked loop. The amount of low frequency jitter that can be tracked is a function of the VCO tuning range. A wider tuning range gives larger accommodation of low frequency jitter. The internal loop control voltage remains small for small phase errors, so the phase shifter remains close to the center of its range, and therefore contributes little to the low frequency jitter accommodation. At medium jitter frequencies, the gain and tuning range of the VCO are not large enough to track the input jitter. In this case, the VCO control voltage becomes large and saturates, and the VCO frequency dwells at one or the other extreme of its tuning range. The size of the VCO tuning range therefore has only a small effect on the jitter accommodation. The delay-locked loop control voltage is now larger; thus, the phase shifter takes on the burden of tracking the input jitter. The phase shifter range, in UI, can be seen as a broad plateau on the jitter tolerance curve. The phase shifter has a minimum range of 2 UI at all data rates.
Rev. B | Page 12 of 24
ADN2819
The gain of the loop integrator is small for high jitter frequencies, so larger phase differences are needed to make the loop control voltage big enough to tune the range of the phase shifter. Large phase errors at high jitter frequencies cannot be tolerated. In this region, the gain of the integrator determines the jitter accommodation. Since the gain of the loop integrator declines linearly with frequency, jitter accommodation is lower with higher jitter frequency. At the highest frequencies, the loop gain is very small and little tuning of the phase shifter can be expected. In this case, jitter accommodation is determined by the eye opening of the input data, the static phase error, and the residual loop jitter generation. The jitter accommodation is roughly 0.5 UI in this region. The corner frequency between the declining slope and the flat region is the closed-loop bandwidth of the delay-locked loop, which is roughly 5 MHz for OC-12, OC-48, and GbE data rates, and 600 kHz for OC-3 data rates.
JITTER PEAKING IN ORDINARY PLL
JITTER GAIN (dB)
ADN2819
Z(s) X(s)
o n psh
d psh c
f (kHz)
Figure 16. Jitter Response vs. Conventional PLL
Rev. B | Page 13 of 24
02999-B-016
ADN2819 FUNCTIONAL DESCRIPTION
MULTIRATE CLOCK AND DATA RECOVERY
The ADN2819 will recover clock and data from serial bit streams at OC-3, OC-12, OC-48, and GbE data rates as well as the 15/14 FEC rates. The output of the 2.5 GHz VCO is divided down in order to support the lower data rates. The data rate is selected by the SEL[2..0] inputs (see Table 5). Table 5. Data Rate Selection
SEL[2..0] 000 001 010 011 100 101 110 111 Rate OC-48 GbE OC-12 OC-3 OC-48 FEC GbE FEC OC-12 FEC OC-3 FEC Frequency (MHz) 2488.32 1250.00 622.08 155.52 2666.06 1339.29 666.51 166.63
Note that it is not expected to use both LOS and slice adjust at the same time. Systems with optical amplifiers need the slice adjust to evade ASE. However, a loss of signal in an optical link that uses optical amplifiers causes the optical amplifier output to be full-scale noise. Under this condition, the LOS would not detect the failure. In this case, the loss of lock signal indicates the failure because the CDR circuitry is unable to lock onto a signal that is full-scale noise.
REFERENCE CLOCK
There are three options for providing the reference frequency to the ADN2819: differential clock, single-ended clock, or crystal oscillator. See Figure 17, Figure 18, and Figure 19 for example configurations.
ADN2819
REFCLKP
LIMITING AMPLIFIER
The limiting amplifier has differential inputs (PIN/NIN) that are internally terminated with 50 to an on-chip voltage reference (VREF = 0.6 V typically). These inputs are normally ac-coupled, although dc-coupling is possible as long as the input common-mode voltage remains above 0.4 V (see Figure 26, Figure 27, and Figure 28 in the Applications Information section). Input offset is factory trimmed to achieve better than 4 mV typical sensitivity with minimal drift. The limiting amplifier can be driven differentially or single-ended.
REFCLKN 100k
BUFFER
100k VCC/2
VCC VCC VCC
XO1 XO2 CRYSTAL OSCILLATOR
02999-B-017
REFSEL
Figure 17. Differential REFCLK Configuration
SLICE ADJUST
The quantizer slicing level can be offset by 100 mV to mitigate the effect of amplified spontaneous emission (ASE) noise by applying a differential voltage input of 0.8 V to SLICEP/N inputs. If no adjustment of the slice level is needed, SLICEP/N should be tied to VCC.
VCC REFCLKP CLK OSC OUT BUFFER REFCLKN NC 100k 100k VCC/2 VCC VCC VCC XO1 XO2 CRYSTAL OSCILLATOR
02999-B-018
ADN2819
LOSS OF SIGNAL (LOS) DETECTOR
The receiver front end level signal detect circuit indicates when the input signal level has fallen below a user adjustable threshold. The threshold is set with a single external resistor from Pin 1, THRADJ, to GND. The LOS comparator trip point versus the resistor value is illustrated in Figure 4 (this is only valid for SLICEP = SLICEN = VCC). If the input level to the ADN2819 drops below the programmed LOS threshold, SDOUT (Pin 45) will indicate the loss of signal condition with a Logic 1. The LOS response time is ~300 ns by design, but it is dominated by the RC time constant in ac-coupled applications. If the LOS detector is used, the quantizer slice adjust pins must both be tied to VCC. This is to avoid interaction with the LOS threshold level.
REFSEL
Figure 18. Single-Ended REFCLK Configuration
Rev. B | Page 14 of 24
ADN2819
ADN2819
VCC
An on-chip oscillator to be used with an external crystal is also provided as an alternative to using the REFCLKN/P inputs. Details of the recommended crystal are given in Table 7.
BUFFER
REFCLKP NC REFCLKN 100k 100k VCC/2 XO1 19.44MHz XO2 CRYSTAL OSCILLATOR
02999-B-019
Table 7. Required Crystal Specifications
Parameter Mode Frequency/Overall Stability Frequency Accuracy Temperature Stability Aging ESR Value Series Resonant 19.44 MHz 100 ppm 100 ppm 100 ppm 100 ppm 50 max
REFSEL
Figure 19. Crystal Oscillator Configuration
The ADN2819 can accept any of the following reference clock frequencies: 19.44 MHz, 38.88 MHz, and 77.76 MHz at LVTTL/ LVCMOS/LVPECL/LVDS levels, or 155.52 MHz at LVPECL/ LVDS levels via the REFCLKN/P inputs, independent of data rate (including Gigabit Ethernet and wrapper rates). The input buffer accepts any differential signal with a peak-to-peak differential amplitude of greater than 100 mV (e.g., LVPECL or LVDS) or a standard single-ended low voltage TTL input, providing maximum system flexibility. The appropriate division ratio can be selected using the REFSEL0/1 pins, according to Table 6. Phase noise and duty cycle of the reference clock are not critical, and 100 ppm accuracy is sufficient. Table 6. Reference Frequency Selection
REFSEL 1 1 1 1 0 REFSEL[1..0] 00 01 10 11 XX Applied Reference Frequency (MHz) 19.44 38.88 77.76 155.52 REFCLKP/N Inactive. Use 19.44 MHz XTAL on Pins XO1, XO2 (pull REFCLKP to VCC)
REFSEL must be tied to VCC when the REFCLKN/P inputs are active, or tied to VEE when the oscillator is used. No connection between the XO pin and the REFCLK input is necessary (see Figure 17, Figure 18, and Figure 19). Note that the crystal should operate in series resonant mode, which renders it insensitive to external parasitics. No trimming capacitors are required.
LOCK DETECTOR OPERATION
The lock detector monitors the frequency difference between the VCO and the reference clock, and deasserts the loss of lock signal when the VCO is within 500 ppm of center frequency. This enables the phase loop, which then maintains phase lock, unless the frequency error exceeds 0.1%. Should this occur, the loss of lock signal is reasserted and control returns to the frequency loop, which will reacquire and maintain a stable clock signal at the output. The frequency loop requires a single external capacitor between CF1 and CF2. The capacitor specification is given in Table 8. Table 8. Recommended CF Capacitor Specification
Parameter Temperature Range Capacitance Leakage Rating Value -40C to +85C >3.0 F <80 nA >6.3 V
LOL 1
1000
500
0
500
1000
fVCO ERROR (ppm)
Figure 20. Transfer Function LOL
Rev. B | Page 15 of 24
02999-B-020
ADN2819
ADN2819
PIN
+
QUANTIZER 0
NIN
CDR
50 VREF 50 1 FROM QUANTIZER OUTPUT 1 50 50 RETIMED DATA CLK
0
VCC
02999-B-021
TDINP/N
LOOPEN BYPASS DATAOUTP/N
CLKOUTP/N SQUELCH
Figure 21. Test Modes
SQUELCH MODE
When the squelch input is driven to a TTL high state, the clock and data outputs are set to the zero state to suppress downstream processing. If desired, this pin can be directly driven by the LOS (loss of signal) detector output (SDOUT). If the squelch function is not required, the pin should be tied to VEE.
TEST MODES: BYPASS AND LOOPBACK
When the bypass input is driven to a TTL high state, the quantizer output is connected directly to the buffers driving the data out pins, thus bypassing the clock recovery circuit (see Figure 21). This feature can help the system deal with nonstandard bit rates.
The loopback mode can be invoked by driving the LOOPEN pin to a TTL high state, which facilitates system diagnostic testing. This connects the test inputs (TDINP/N) to the clock and data recovery circuit (per Figure 21). The test inputs have internal 50 terminations, and can be left floating when not in use. TDINP/N are CML inputs and can only be dc-coupled when being driven by CML outputs. The TDINP/N inputs must be ac-coupled if driven by anything other than CML outputs. Bypass and loopback modes are mutually exclusive: only one of these modes can be used at any given time. The ADN2819 is put into an indeterminate state if both the BYPASS and LOOPEN pins are set to Logic 1 at the same time.
Rev. B | Page 16 of 24
ADN2819 APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal performance. The high speed inputs, PIN and NIN, are internally terminated with 50 to an internal reference voltage (see Figure 24). A 0.1 F capacitor is recommended between VREF, Pin 4, and GND to provide an ac ground for the inputs. As with any high speed mixed-signal design, take care to keep all high speed digital traces away from sensitive analog nodes.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane to both analog and digital grounds is recommended. The VEE pins should be soldered directly to the ground plane to reduce series inductance. If the ground plane is an internal plane and connections to the ground plane are made through vias, multiple vias may be used in parallel to reduce the series inductance, especially on Pins 33 and 34, which are the ground returns for the output buffers. Use of a 10 F electrolytic capacitor between VCC and GND is recommended at the location where the 3.3 V supply enters the PCB. Use of 0.1 F and 1 nF ceramic chip capacitors should be placed between IC power supply VCC and GND as close as possible to the ADN2819 VCC pins. Again, if connections to the supply and ground are made through vias, the use of multiple vias in parallel will help to reduce series inductance, especially on Pins 35 and 36, which supply power to the high speed CLKOUTP/N and DATAOUTP/N output buffers. Refer to the schematic in Figure 22 for recommended connections.
Soldering Guidelines for Chip Scale Package
The lands on the 48-lead LFCSP are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a central exposed pad. The pad on the printed circuit board should be at least as large as this exposed pad. The user must connect the exposed pad to analog VCC. If vias are used, they should be incorporated into the pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm; the via barrel should be plated with 1 oz. copper to plug the via.
Transmission Lines
Use of 50 transmission lines are required for all high frequency input and output signals to minimize reflections, including PIN, NIN, CLKOUTP, CLKOUTN, DATAOUTP, and DATAOUTN (also REFCLKP/N for a 155.52 MHz REFCLK). It is also recommended that the PIN/NIN input traces are matched in length and that the CLKOUTP/N and DATAOUTP/N traces are matched in length. All high speed CML outputs, CLKOUTP/N and DATAOUTP/N, also require 100 back termination chip resistors connected between the output pin and VCC. These resistors should be placed as close as possible to the output pins. These 100 resistors are in parallel with on-chip 100 termination resistors to create a 50 back termination (see Figure 23).
Rev. B | Page 17 of 24
ADN2819
VCC 4 x 100 50 TRANSMISSION LINES CLKOUTP VCC 10F 0.1F 1nF C CLKOUTN DATAOUTP DATAOUTN
48 47 46 45 44 43 42 41 40 39 38 37 RTH THRADJ VCC VCC 0.1F 50 TIA 50 CIN VCC C 19.44MHz 1nF 0.1F VEE VREF PIN NIN SLICEP SLICEN VEE LOL XO1 XO2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1nF 0.1F EXPOSED PAD TIED OFF TO VCC PLANE WITH VIAS 36 35 34 33 32 31 30 29 28 27 26 25 VCC VCC VEE VEE SEL0 SEL1 SEL2 VEE VCC VEE VCC CF2 1nF 0.1F VCC C 1nF 0.1F VCC
ADN2819
SQUELCH
CLKOUTN
CLKOUTP
LOOPEN
BYPASS
SDOUT
VCC
VEE
VEE
VEE
DATAOUTN
DATAOUTP
REFSEL
VEE
VEE
VEE
REFSEL1
REFCLKN
REFCLKP
NC
NC
VCC
NC
C
C
REFSEL0
TDINN
TDINP
VCC
CF1
4.7F (SEE TABLE 8 FOR SPECS)
1nF
0.1F
Figure 22. Typical Application Circuit
VCC VCC VTERM 100 100 100 100 0.1 F 50 50
VCC 50 TIA CIN
ADN2819
PIN
50
CIN
NIN
0.1 F
50 50 VTERM
02999-B-023
50 VREF
50
ADN2819
0.1 F
02999-B-022
VCC
Figure 23. AC-Coupled Output Configuration Figure 24. AC-Coupled Input Configuration
Rev. B | Page 18 of 24
02999-B-024
ADN2819
CHOOSING AC-COUPLING CAPACITORS
The choice of ac-coupling capacitors at the input (PIN, NIN) and output (DATAOUTP, DATAOUTN) of the ADN2819 must be chosen such that the device works properly at the lower OC-3 and higher OC-48 data rates. When choosing the capacitors, the time constant formed with the two 50 resistors in the signal path must be considered. When a large number of consecutive identical digits (CIDs) are applied, the capacitor voltage can drop due to baseline wander (see Figure 23), causing pattern dependent jitter (PDJ). For the ADN2819 to work robustly at both OC-3 and OC-48, a minimum capacitor of 1.6 F to PIN/NIN and 0.1 F on DATAOUTP/DATAOUTN should be used. This is based on the assumption that 1000 CIDs must be tolerated and that the PDJ should be limited to 0.01 UI p-p.
V1
CIN
ADN2819
V2 PIN 50 VREF
COUT DATAOUTP CDR COUT DATAOUTN
+
LIMAMP
TIA V1b CIN V2b NIN
50
1
V1 V1b V2 V2b VDIFF
2
3
4
VREF VTH
VDIFF = V2-V2b VTH = ADN2819 QUANTIZER THRESHOLD
NOTES 1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS 0. 2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE VREF LEVEL, WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS. 3. WHEN THE BURST OF DATA STARTS AGAIN,THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO THE INPUT LEVELS, CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES, EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELLED OUT. THE QUANTIZER WILL NOT RECOGNIZE THIS AS A VALID STATE. 4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2819. THE QUANTIZER WILL BE ABLE TO RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT.
Figure 25. Example of Baseline Wander
Rev. B | Page 19 of 24
02999-B-025
ADN2819
DC-COUPLED APPLICATION
The inputs to the ADN2819 can also be dc-coupled. This may be necessary in burst mode applications where there are long periods of CIDs and baseline wander cannot be tolerated. If the inputs to the ADN2819 are dc-coupled, care must be taken not to violate the input range and common-mode level requirements of the ADN2819 (see Figure 26, Figure 27, and Figure 28). If dc-coupling is required, and the output levels of the TIA do not adhere to the levels shown in Figure 27 and Figure 28, there needs to be level shifting and/or an attenuator between the TIA outputs and the ADN2819 inputs.
VCC 50 TIA
ADN2819
PIN
50
NIN
50 VREF
50
Figure 26. ADN2819 with DC-Coupled Inputs
INPUT (V)
LOL TOGGLING DURING LOSS OF INPUT DATA
If the input data stream is lost due to a break in the optical link (or for any reason), the clock output from the ADN2819 will stay within 1000 ppm of the VCO center frequency as long as there is a valid reference clock. The LOL pin toggles at a rate of several kHz because the LOL pin toggles between a Logic 1 and a Logic 0, while the frequency loop and phase loop swap control of the VCO. The chain of events is as follows: * * The ADN2819 is locked to the input data stream; LOL = 0. The input data stream is lost due to a break in the link. The VCO frequency drifts until the frequency error is greater than 1000 ppm. LOL is asserted to a Logic 1 as control of the VCO is passed back to the frequency loop. The frequency loop pulls the VCO to within 500 ppm of its center frequency. Control of the VCO is passed back to the phase loop and LOL is deasserted to a Logic 0. The phase loop tries to acquire, but there is no input data present so the VCO frequency drifts. The VCO frequency drifts until the frequency error is greater than 1000 ppm. LOL is asserted to a Logic 1 as control of the VCO is passed back to the frequency loop. This process is repeated until a valid input data stream is re-established.
V p-p = PIN - NIN = 2 x VSE = 10mV AT SENSITIVITY PIN VSE = 5mV MIN VCM = 0.4V MIN (DC-COUPLED)
02999-B-027
NIN
Figure 27. Minimum Allowed DC-Coupled Input Levels
INPUT (V) V p-p = PIN - NIN = 2 x VSE = 2.4V MAX PIN
VSE = 1.2V MAX
*
VCM = 0.6V (DC-COUPLED)
02999-B-028
NIN
* *
Figure 28. Maximum Allowed DC-Coupled Input Levels
Rev. B | Page 20 of 24
02999-B-026
0.1 F
ADN2819 OUTLINE DIMENSIONS
7.00 BSC SQ 0.60 MAX 0.60 MAX
37 36
0.30 0.23 0.18
48 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
6.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
5.25 5.10 SQ 4.95
0.50 0.40 0.30
25 24
12 13
0.25 MIN 5.50 REF
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC
SEATING PLANE
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 29. 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 mm x 7 mm Body (CP-48) Dimensions shown in millimeters
ORDERING GUIDE
Model ADN2819ACP-CML ADN2819ACP-CML-RL ADN2819ACPZ-CML1 ADN2819ACPZ-CML-RL1 EVAL-ADN2819-CML Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 48-Lead LFCSP 48-Lead LFCSP 48-Lead LFCSP 48-Lead LFCSP Evaluation Board Package Option CP-48 CP-48 CP-48 CP-48
1
Z = Pb Free.
Rev. B | Page 21 of 24
ADN2819 NOTES
Rev. B | Page 22 of 24
ADN2819 NOTES
Rev. B | Page 23 of 24
ADN2819 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02999-0-5/04(B)
Rev. B | Page 24 of 24

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